I accept that Kicad is not specific to any one manufacturer so I’m not expecting the design rules to match to JLCPCB rules. In all cases, these minimums are greater than 0.127mm - for example, minimum clearance via to track is 0.254mm. However, JLCPCB also has minimum clearances for via to via, pad to pad, via to track, pad to track etc. It also has a minimum hole to hole of 0.25mm although JLCPCBs minimum is 0.5mm (that’s easily fixed.) I have used the template kindly provided by Seth_h which has a clearance of 0.127mm and this correlates to JLC’s minimum spacing for tracks - there must be at least 0.127mm between the nearest edges of tracks. In Kicad board setup, Net Classes, I can set a ‘Clearance’ but it’s not clear what the clearance value refers to in respect to the overall set of minimum clearances JLC give. This seems like a good thread to continue a discussion on JLCPCB rules.
Hole Size Tolerance- Where to change that?Īnular Ring -Where to change that?Īlso I know what µ stands for but what is the difference between “Via Size” and “µVia Size” and when to apply that. Via to Trace- Where to change that?ĭrill Hole Size- Where to change that? If I know that I will know what I’m doing eheh. I just don’t know where to change that value.
First of all Thank you Both and for the replies.Ībout the templates i was looking for one yesterday and here it is thanks to you what I wanted was a bit of a 1-to-1 conversion because I know what is a Via and Trace.
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